A voltage regulator (constant voltage circuit) includes a differential amplifier unit that receives a reference voltage Vref at a non-inverting input thereof, an output transistor, and voltage dividing resistors that perform voltage division of an output of the output transistor. By negatively feeding back an output of the voltage regulator to an inverting input of the differential amplifier unit, a constant voltage is output at an output terminal of the voltage regulator. The differential amplifier unit and the output transistor of the voltage regulator each have a pole (at which a denominator of a transfer function equals 0) and a frequency characteristic in which a gain decreases and a phase is delayed with the increase of the frequency from the pole. Assume a phase margin (Phase Margin: P. M.) is small when the gain has decreased to 0 dB. Then, an operation of the circuit becomes unstable. If the gain assumes 0 dB or more (when the gain assumes 1 or more) and the phase is delayed by 180 degrees, the circuit oscillates. The phase margin (P. M.) indicates how much margin is present from the phase of −180 degrees when the gain is 0 dB in the frequency characteristic.
A phase compensation circuit formed of a phase compensation capacitor and a phase compensation resistance is connected to a non-inverting amplifier circuit (non-inverting input type negative feedback amplifier circuit) such as the voltage regulator or a voltage follower so as to prevent oscillation and stabilize operation. By doing so, a zero (at which a numerator of the transfer function equals 0) having a property opposite to the pole is generated to ensure the phase margin. A frequency corresponding to a bending point on a frequency characteristic of the non-inverting amplifier circuit is referred to as the pole. The phase is delayed by 90 degrees from 0.1 fp to 10 fp, where fp is a pole frequency. With the increase of a frequency occurs from a zero-point frequency (=1/(2πCR)), the phase advances. For example, the phase advances by 90 degrees from 0.1 fz to 10 fz, where fz is a zero point frequency. This phase advancement cancels a phase delay caused by the pole (performs phase compensation), ensures a phase margin, and prevents oscillation. In this way, the phase is compensated in the non-inverting amplifier circuit.
The voltage regulator as the non-inverting amplifier circuit will be described below. FIG. 4 is a diagram showing a circuit configuration of the voltage regulator related to the invention of this application. FIG. 4 is used for explaining problems and an analysis of this application, which will be described later.
Referring to FIG. 4, a voltage regulator 10′ comprises:    (A) an nMOS transistor (constant current source transistor) NM3 which has a source connected to the ground and has a gate supplied with a bias voltage VB;    (B) a pair of nMOS transistors NM1 and NM2 which have sources coupled in common to a drain of the nMOS transistor NM3 and have gates respectively supplied with a reference voltage Vref (supplied from a reference voltage circuit not shown) and a feedback voltage (voltage obtained by voltage-dividing an output terminal voltage Vout by resistors Rf and Rs), and which forms a differential pair;    (C) a pMOS transistor PM1 which has a source connected to a power supply VDD and has a drain connected to a drain of the nMOS transistor NM1 and a pMOS transistor PM2 which has a source connected to the power supply VDD, has a gate connected to a gate of the pMOS transistor PM1, and has the gate and a drain thereof connected to each other to a drain of the nMOS transistor NM2 (the pMOS transistors PM1 and PM2 being a load circuit for the differential pair and forming a current mirror);    (D) a pMOS transistor PM3 (also referred to as an output transistor or an output driver) which has a source connected to the power supply VDD, has a gate connected to the drain of the nMOS transistor NM1, and has a source connected to an output terminal OUT;    (E) a resistor Rf (also referred to as a feedback resistor) and a resistor Rs which are connected between the source of the pMOS transistor PM3 and the ground and which form voltage-dividing resistors; and    (F) a resistor Rz (phase compensation resistance, which produces the zero of a frequency characteristic, also termed as a zero-point resistor) and a capacitor Cc connected in series between a gate node N1 of the pMOS transistor PM3 and a connection node (node N2) of the resistor Rf and the resistor Rs.
The nMOS transistors NM1 and NM2 (differential pair), nMOS transistor NM3 (constant current source), and pMOS transistors PM1 and PM2 (load circuit) form a differential amplifier unit. The pMOS transistor PM3 and the resistors Rf and Rs form an output stage unit. The resistor Rz and the capacitor Cc form a phase compensation unit. An external circuit (load circuit) is connected to the output terminal OUT. A compensation capacitor C is externally connected between the output terminal OUT and the ground.
Assuming that a voltage at the output terminal OUT is Vout in the circuit in FIG. 4, from the following equation (1), Vout is given by the following equation (2).
                    Vref        =                  Vout          ×                      Rs                          Rf              +              Rs                                                          (        1        )                                Vout        =                  Vref          ×                      (                          1              +                              Rf                Rs                                      )                                              (        2        )            
Based on this equation (2), the well-known gain formula of the non-inverting amplifier circuit is derived as follows:
                    Gain        =                              Vout            Vref                    =                      1            +                          Rf              Rs                                                          (        3        )            
The frequency characteristic of the circuit in FIG. 4 depends on an output current (load current) Iout of the pMOS transistor PM3 (output transistor). FIG. 5A is a diagram which schematically shows the frequency characteristic of the circuit in FIG. 4. An AC signal is supplied (to the gate of the nMOS transistor NM1) in FIG. 4 as an input, instead of the reference voltage Vref that is a DC signal, with the frequency being swept, and a gain characteristic and a phase characteristic with respect to a frequency are plotted. In FIG. 5A, a horizontal axis indicates the frequency, a left-side vertical axis indicates a gain, and a right-side vertical axis indicates a phase. The frequency characteristic can be obtained by circuit simulation as well. FIG. 5B shows frequency characteristics of a gain and a phase in case the output current Iout in FIG. 4 is set to be larger than in FIG. 5A (wherein a horizontal axis indicates a frequency, a left-side vertical axis indicates the gain, and a right-side vertical axis indicates the phase).
Referring to FIGS. 5A and 5B, p0, p1, and p2 respectively denote first, second, and third poles, and z0 denotes a zero (zero-point frequency). A phase (Phase) corresponding to the gain of 0 dB (refer to arrows) corresponds to a phase margin (PM), which shows to what extent there is a margin from −180 degrees. When the gain is 0 dB (factor 1) and the phase is rotated by −180 degrees or less, the non-inverting amplifier circuit may possibly oscillate.
When the output current Iout increases as shown in FIG. 5B, the phase margin decreases more than in FIG. 5A. If the output current Iout further increases, the zero-point frequency z0 increases in substantial proportion to the output current Iout. Thus, it is difficult to cancel a phase delay caused by the pole.
FIG. 5C is a diagram showing relationships among the output current (load current) Iout of the voltage regulator in FIG. 4 (plotted on a horizontal axis), gain (Gain), output voltage Vout, and phase margin (P. M.) (plotted on a vertical axis). FIGS. 5A to 5C are prepared by the inventor of this invention.
When a range of the output current Iout is wide as shown in FIG. 5C, frequency characteristic adjustment becomes difficult. Among the frequency characteristics, a characteristic of phase margin (P. M.) in particular is greatly influenced by the output current Iout. As the output current Iout increases, the characteristic of phase margin (P. M) attenuates. On an upper limit side of the output current Iout, the phase margin approaches a specification lower limit (lower limit for compensating for an operation). When the output current Iout of the pMOS transistor PM3 increases, the voltage Vout of the output terminal OUT decreases (due to a voltage drop from the supply voltage VDD, caused by an impedance of the output terminal out, for example). Accordingly, when the output current Iout increases, the gain=Vout/Vref is reduced, as shown in FIG. 5C.
Patent Document 1 discloses a voltage regulator including a phase compensation control circuit. This phase compensation control circuit is provided for a phase compensation circuit. In the phase compensation circuit, a phase of a feedback voltage VFB of an operational amplifier is advanced, thereby performing phase compensation. In the phase compensation control circuit, short-circuit control of a phase compensation resistance is performed according to an output current of an output driver (transistor), detected by a current detection unit. The phase compensation control circuit thereby performs control so that a time constant of the phase compensation circuit is changed. Then, the phase compensation control circuit performs control of a frequency at which phase compensation is performed on the feedback voltage VFB. Referring to Patent Document 1, when the output current is determined to be a predetermined value or more by a current detection circuit, an nMOS transistor inserted in series with a capacitance between a drain of the output driver and a voltage division node between voltage dividing resistors is controlled to be turned on. A time constant of a phase compensating capacitance is thereby reduced. Even if a frequency at which a phase delay is generated by the output driver transistor is shifted to a high frequency side, a frequency at which phase compensation is performed by the phase compensation circuit is shifted to the high frequency side. A phase margin is thereby increased. Patent Document 1 JP Patent Kokai Publication No. JP-P-2002-297248A